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wireless components rf/if double pll frequency synthesizer pmb 2347 version 1.1 specification august 1999 preliminary
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 25.10.99. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history: current version: 08.99 previous version:data sheet page (in previous version) page (in current version) subjects (major changes since last revision)
productinfo product info wireless components specification, august 1999 package pmb 2347 preliminary productinfo general description the pmb 2347 is a rf/if double pll frequency synthesizer implemented in infineon high speed bicmos technol- ogy b6hfc. the device contains two plls with integrated prescalers espe- cially designed for use in battery pow- ered radio equipment and mobile telephones. primary applications are single- and dual-band digital cellular systems e.g. gsm, pcn (dcs 1800) and pcs systems. features n operation range 2.7 to 5.0 v n low operating current consumption n programmable power down modes n high input sensitivity and high input frequencies: pll1 (rf): 2.8 ghz pll2 (if): 500 mhz n programmable dual modulus prescaler divide ratio: pll1: 1:64/65 or 1:32/33 pll2: 16/17 or 1:8/9 dividing ratios: a counters: pll1: 0 to 63 pll2: 0 to 15 n counters: pll1: 3 to 16,383 pll2: 3 to 16,383 r counters 3 to 16,383 for pll1 and pll2 n fast phase detectors and charge pump outputs without dead zone n high phase noise performance n switchable polarity and program- mable phase detector currents n external reference current setting for pd outputs n fast serial 3-wire bus interface with low threshold voltage schmitt-trig- ger inputs for interfacing with low voltage baseband circuits n two data registers in pll2 for fast if band switching n a programmable multi-functional output port for lock detect (quasi- digital lock detect) and test mode ordering information type ordering code package pmb 2347 p-tssop-20
1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 typical supply current icc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.4 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 serial control data format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3 serial control data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4 input sensitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5 charge pump currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.6 threshold voltages of schmitt-trigger input . . . . . . . . . . . . . . . . . . 5-16
2 product description 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 contents of this chapter
product description 2 - 2 pmb 2347 preliminary wireless components specification, august 1999 2.1 overview the pmb 2347 is a rf/if double pll frequency synthesizer implemented in infineon high speed bicmos technology b6hfc. the device contains two plls with integrated prescalers especially designed for use in battery powered radio equipment and mobile telephones. primary applications are single- and dual-band digital cellular systems e.g. gsm, pcn (dcs 1800) and pcs sys- tems. 2.2 features n operation range 2.7 to 5.0 v n low operating current consumption n programmable power down modes n high input sensitivity and high input frequencies: pll1 (rf): 2.8 ghz pll2 (if): 500 mhz n programmable dual modulus prescaler divide ratio: pll1: 1:64/65 or 1:32/33 pll2: 16/17 or 1:8/9 dividing ratios: a counters: pll1: 0 to 63 pll2: 0 to 15 n counters: pll1: 3 to 16,383 pll2: 3 to 16,383 r counters 3 to 16,383 for pll1 and pll2 n fast phase detectors and charge pump outputs without dead zone n high phase noise performance n switchable polarity and programmable phase detector currents n external reference current setting for pd outputs n fast serial 3-wire bus interface with low threshold voltage schmitt-trigger inputs for interfacing with low voltage baseband circuits n two data registers in pll2 for fast if band switching n a programmable multi-functional output port for lock detect (quasidigital lock detect) and test mode
product description 2 - 3 pmb 2347 preliminary wireless components specification, august 1999 2.3 package outlines p-tssop-20
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 2 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3 standby condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 4 divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 5 prescaler divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 6 fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 7 phase detector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 contents of this chapter
functional description 3 - 2 pmb 2347 preliminary wireless components specification, august 1999 3.1 pin configuration pin_config.wmf figure 3-1 pin configuration 3.2 pin definition and function vcc2 vpd2 cp2 gnd1 if ifx gnd2 ri rext ld/fo vcc1 vpd1 cp1 gnd1 rf rfx gnd2 en da clk 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pmb 2347 table 3-1 pin definition and function pin no. symbol equivalent i/o-schematic function 1 vcc1 positive supply voltage for cmos circuitry 2 vpd1 positive supply voltage for charge pump of pll1 3 cp1 pll1 charge pump output phase detector tristate charge pump output pd output equivalent esd *2pf cp1 3
functional description 3 - 3 pmb 2347 preliminary wireless components specification, august 1999 4 gnd1 ground for cmos cir- cuitry 5 6 rf1 rfx rf frequency input 1 rf input with highly sen- sitive preamplifier for pll1. ac coupling must be set up. rf frequency input (inverted) rf input with highly sen- sitive preampifier for pll1. ac coupling must be set up 7 gnd1 ground for bipolar cir- cuitry 8 en 3-wire bus input: enable enable input of the serial control interface with schmitt-trigger input stage. when en=h the input signals clk and da are disabled. when en=l the serial control interface is enabled. the received data are transferred to the registers with the positive edge of the en-signal. 9 da 3-wire bus input: data data input of the serial control interface with schmitt-trigger input stage.the serial data are read into the internal shift register with the positive edge of clk. rf/if 5/16 rfx/ifx 6/15 rf and if input equivalent esd *2pf 560 w 75k w serial control input equivalent clk 8 esd *2pf 560 w 75k w serial control input equivalent da 9
functional description 3 - 4 pmb 2347 preliminary wireless components specification, august 1999 10 clk 3-wire bus input: clock clock input of the serial control interface with schmitt-trigger input stage 11 ld/fo lock detector output unipolar output of the phase detector in the form of a pulse-width modulated signal. in the locked state the output signal is at h-level. in standby mode the output is resistive. for test purpose the push pull output fo is enabled. 12 rext cp& prescaler refer- ence current setting external resistor for cp & prescaler reference cur- rent setting. 13 ri reference frequency input input with highly sensi- tive preamplifier. with small input signals ac coupling must be set up, where dc coupling can be used for large input signals. 14 gnd2 ground for bipolar cir- cuitry esd *2pf 560 w 75k w serial control input equivalent en 10 esd *2pf ld/fo ld as lock detector 11 osw output equivalent esd 2pf rext 12 560 w esd 2pf stdby /stdby ri 500k w 13 ri input equivalent
functional description 3 - 5 pmb 2347 preliminary wireless components specification, august 1999 15 16 ifx if if frequency input (inverted) if input with highly sensi- tive preampifier for pll2. ac coupling must be set up. if frequency input if input with highly sensi- tive preampifier for pll2. ac coupling must be set up. 17 gnd1 ground for cmos cir- cuitry 18 cp2 phase detector tristate charge pump output for pll2 19 vpd2 positive supply voltage for charge pump 2. 20 vcc2 positive supply voltage for bipolar circuitry rf/if 5/16 rfx/ifx 6/15 rf and if input equivalent pd output equivalent esd *2pf cp2 18
functional description 3 - 6 pmb 2347 preliminary wireless components specification, august 1999 3.3 functional block diagram funct_block.wmf figure 3-2 functional block diagram 376623 4 bit a-counter shift register data reg. 2 data reg. 1 14 bit n-counter shift register data reg. 2 data reg. 1 modulus control shadow reg. data reg. 14 bit r1-counter 64/65 32/33 6 bit a-counter shift register data reg. 14 bit n-counter shift register shadow reg. data reg. modulus control phase detector shift register ld fo vcc1 pll1 (rf) pll2 (if) gnd2 vpd1 gnd1 pd1 rf clk en rfx da vcc2 gnd2 vpd2 gnd1 pd2 if ld/fo ri ifx rext serial control logic phase detector shadow reg. mod1 mod1 data reg. 14 bit r1-counter shift register 16/17 8/9 mod2 multiplexer multiplexer bias iref dec 1 2 3 4 10 9 8 7 6 5 20 19 18 17 11 12 13 14 15 16
functional description 3 - 7 pmb 2347 preliminary wireless components specification, august 1999 3.4 circuit description 1. general description the pmb 2347 consists of two fully programmable plls, one for the rf and one for the if frequency range. each pll contains a high frequency dual mod- ulus prescaler, an a- and a n-counter with dual modulus control logic, a refer- ence- (r-) counter, and a phase detector with charge pump output. the two synthesizers are controlled via the common serial 3-wire interface. the reference frequency is applied at the common ri-input and divided by the r-counter of each pll. its maximum value is 45 mhz. the rf and if input fre- quencies will be divided by the corresponding prescalers with a programmable 32/32 or 64/65 (rf) and 8/9 or 16/17 (if) divide ratio and the following program- mable a/n-counters. the maximum rf frequency value is 2.8 ghz and 500 mhz for the if frequency. the phase and frequency detectors with the charge pumps have a linear oper- ating range without a dead zone for very small phase deviations. the multifunctional output port ld/fo can be programmed as lock detector and test output. 2. programming programming of the ic is done via the serial data interface. the content of the bus telegram (serial data format) is assigned to the functional units according to the address. the most significant bit (msb) of the serial data formats is shifted first. the short control data format allows a fast pd-current change. the long control data format allows the programming of asynchronous or syn- chronous data acquisition of pll1 (rf), 4 different pd-output current modes for the pll1 and 1 pd-output current modes for pll2, polarity setting of the pd- output signals, 2 standby modes, charge pump pulse width and the prescaler divide ratio. the a/n-counter data format of pll1 contains the a/n-counter value.. the data format of pll2 comprise the counter values as well. the r-counter data format contains the r-counter values. the pll1 (rf) of pmb 2347 offers the possibility of synchronous counter and charge pump current programming to avoid phase errors at the phase detector when r- and a-/n-counter are programmed one after another or the charge pump current is altered. asynchronous mode: the serial data is written directly to the data registers of the addressed counter with the enable pulse. as each counter is loading the new starting value after it is decremented to ?zero, the counters changes therefore their counter values asynchronously to the others.
functional description 3 - 8 pmb 2347 preliminary wireless components specification, august 1999 synchronous mode (only for rf): in this mode counter programming is controlled by the r- and n-counters. the serial data (exception: higher part of long control data format) is first written with the enable pulse to the corresponding shadow registers. from there the values for r-counter, a-/n-counter and charge pump current values of short/long con- trol data format are loaded into the corresponding data register when the n- counter reaches ?zero+1. therefore the change of all counter states is syn- chronised to the reloading of the n-counter to avoid additional phase error caused by the programming. the transfer of the charge pump current values into the corresponding data register is tied to the n-counter loading, but follows the loading of the n-data register in the distance of one n-counter dividing ratio. this guarantees that a new pd-current value becomes valid at the same time when the counters are loaded with the new data. synchronous programming sequence: 1.setting of synchronous counter programming by bit c13 of long control data format. 2.programming of the r-counter, and optional short control data format. with the enable signal data is loaded into the shadow registers. 3.programming of the a/n-counter. data is loaded into shadow registers, the en-signal starts the synchronous transfer to the data registers. synchronous data programming is of especial advantage, when large fre- quency steps are to be made in a short time. for this purpose a high reference frequency can be programmed in order to achieve rapid C rough C transient response. this method increases the fundamental frequency by nearly the square root of the reference frequency ratio and therefore the settling time is reduced. when rough lock is achieved, another synchronous data transfer is needed to switch back to the original channel spacing. a fine lock in will finish the total step response. it may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. espe- cially for gsm, pcn (dcs 1800) and pcs systems the synchronous mode should be used to achieve best performance of the pmb 2347. 3. standby condition (power down) each pll of the pmb 2347 has two programmable standby modes to reduce the current consumption (standby 1, standby 2). standby 1: the corresponding pll is switched off, the current consumption is reduced below 1 m a. standby 2: the corresponding counters, the charge pump and the outputs are switched off. only the preamplifier of ri-input stays active. (see standby table)
functional description 3 - 9 pmb 2347 preliminary wireless components specification, august 1999 4. divide ratio programming the frequency of an external vco controlled by the pmb 2347 is given below: with . f vco : frequency of the external vco f ri : reference frequency n: divide ratio of the n-counter a: divide ratio of the a-swallow counter p: divide ratio of the prescaler r: divide ratio of the r-counter m=p*n+a: total divide ratio note: for continous frequency steps following condition is necessary 5. prescaler divide ratio for the highest input frequencies of the prescalers the larger divide ratio is nec- essary: rf-pll: 64/65 for frequencies greater 1500 mhz if-pll: 16/17 for frequencies greater 375 mhz 6. fast wake-up programming when the circuit is connected to the supply voltage all registers are undefined. due to the fact that each counter is loading its new start value after it is decre- mented to ?zero, the start-up time of the counters with the programmed values is too long for some applications. if the counters are programmed in standby mode 2 and the plls are switched afterwards in operating mode, the counters are starting immediatly with the programmed values. therefore following data transfer sequence is recommended: table 3-2 fast wake up data transfer sequence step serial data transfer sequence 1 long control word: asynchronous mode, standby2 2 r-counter 3 a-/n-counter 4 long control word: synchronous mode, operating mode f vco pn () a + [] f ri r ------ - m r ---- - f ri == an pn a + [] pp1 C () 3
functional description 3 - 10 pmb 2347 preliminary wireless components specification, august 1999 7. phase detector outputs the timing diagram is valid for pll1 and pll2. ri cp cp ld (ri:r) (rf1:m) positive polarity n-channel frequency i v > i r i v leading frequency i v = i r lock state frequency i v < i r i v lagging i r i v rf1/2 (rf2:m) negative polarity p-channel tri-state n-channel p-channel tri-state
4 applications 4.1 hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 contents of this chapter
applications 4 - 2 pmb 2347 preliminary wireless components specification, august 1999 4.1 hint more information about application see in separate document application note pmb 2347 .
5 reference 5.1 electrical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 serial control data format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3 serial control data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.4 input sensitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5 charge pump currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.6 threshold voltages of schmitt-trigger input . . . . . . . . . . . . . . . . . . 5-16 contents of this chapter
reference 5 - 2 pmb 2347 preliminary wireless components specification, august 1999 5.1 electrical data 5.1.1 absolute maximum ratings warning the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. table 5-1 absolute maximum ratings parameter symbol limit values unit remarks min max supply voltage v cc1/2 -0.3 5.5 v input voltage 9 i -0.3 9 && +0.3 v output voltage 9 o gnd 9 && v total power dissipation 3 tot 300 mw ambient temperature 7 a -40 85 c in operation storage temperature 7 stg -50 125 c thermal resistance 5 thja 170 k/w esd integrity (according to mil 883 method 3015.7) except pins vpd1[2] and vpd2[19] 9 esd 0.5 kv preliminary
reference 5 - 3 pmb 2347 preliminary wireless components specification, august 1999 5.1.2 operating range within the operational range the ic operates as described in the circuit description. the ac/dc characteristic limits are not guaranteed. 5.1.3 typical supply current i cc 1) ? rf1 = 900mhz, v rf = 150mvrms, ? rf2 = 420mhz, v rf2 = 150mvrms,? ri = 10mhz, v ri = 150mvrms, i cp1 = 4.0ma, i cp2 = 2.0ma, iref = 100 m a table 5-2 operating range, vcc1/2= 2.7v - 5.0v, t amb =-40c ... + 85c typical parameter symbol limit values unit test conditions item min max supply voltage 9 && /2 2.7 5.0 v input frequency rf ? rf 250 2800 mhz 9 && 1/2 = 3.6v input frequency if ? if 100 500 mhz input reference frequency ? ri 1 45 mhz cp-output current of pll1 / , cp1 / 4 +20% ma cp-output current of pll2 / , cp2 / 1 +20% ma cp-output voltages 9 cp1/2 0.5 9 3' 1/2 - 0.5 v ambient temperature 7 a -40 85 c table 5-3 typical supply current i cc parameter symbol limit values unit test conditions item min typ max supply voltage 9 && /2 3.6 vr ext = 12k supply current: note 1) pll1 & pll2 active , cc1/2 -20% 8.0 +20% ma v cc1/2 = 3.6v pll1 active, pll2 standby , cc1/2 -20% 5.9 +20% ma pll1 standby2, pll2 active , cc1/2 -20% 3.2 +20% ma pll1 & pll2 standby 2 , cc1/2 120 a pll1 & pll2 standby 1 , cc1/2 < 1 a
reference 5 - 4 pmb 2347 preliminary wireless components specification, august 1999 5.1.4 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the spec- ified supply voltage and ambient temperature range. typical characteristics are the median of the production. table 5-4 ac/dc characteristics with vcc 1/2 =2.7 .. 5.0 v, ambient temperature t amb = -40c to 85c sym- bol limit values unit test conditions l item min typ max input signals da, clk, en (schmitt-trigger input stage) h-input voltage 9 ih 0.7 9 cc 9 cc v l-input voltage 9 il 0.3 9 cc v input capacity & i 5pf h-input current , h 10 a v i =v cc2 =3.6v 2.3 l-input current , l -10 a v i =gnd 2.4 input signal ri input voltage 9 i 100 mvrms f= 4 - 45 mhz, v cc1 =3.6v 2.10 slew rate 4v/s v cc1 =2.7 - 5.0 v input capacity & i 3pf h-input current , h 30 a v i =v cc1 =3.6v 2.13 l-input current 9 i -30 a v i =gnd input signals rf input voltage 9 i mvrms f = 150-450 mhz 3.1 3 i -12 +6 dbm input voltage 9 i mvrms f = 450-2500 mhz 3.2 3 i -20 +4 dbm input voltage 9 i mvrms f = 2500-2800 mhz 3 i -10 -2.5 dbm input signals if input voltage 9 i mvrms f = 100 - 350 mhz 4.1 3 i -16 +4 dbm input voltage 9 i mvrms f = 350 - 450 mhz 4.2 3 i -25 -5 dbm input voltage 9 i mvrms f = 450 - 600 mhz 3 i -25 -15 dbm
reference 5 - 5 pmb 2347 preliminary wireless components specification, august 1999 table 5-4 ac/dc characteristics with vcc 1/2 =2.7 .. 5.0 v, ambient temperature t amb = -40c to 85c (continued) sym- bol limit values unit test conditions item min typ max output current icp1 "1.2 ma" , cp1 -20% 1.2 +20% ma v pd1 =5.0v, v cp1= v pd1 /2 i ref =100a *guaranteed by design 5.1 "2.0 ma" , cp1 -20% 2.0 +20% ma 5.2 "2.8 ma" , cp1 -20% 2.8 +20% ma 5.3 "4.0 ma" , cp1 -20% 4.0 +20% ma 5.4 "tristate" / , cp1 / 0.1 10*) na 5.5 output current icp2 "1.0 ma" , cp2 -20% +20% ma v pd2 =3.6v, v cp1 =vpd1/2 i ref =100a *guaranteed by design "tristate" / , cp2 / 0.1 10*) na output current offset cp1 & cp2 cp supply voltage v pd1/2 2.7 3.6 5.0 v v cp1 /2 = v pd2 /2 cp current offsett , cp-off -4 0 +13 % magnitude variation "+1.2 ma" , cpmv 4% v pd1 =5v, v cp1 = v pd1 /2 iref=100 a see chargepump specification for details on spurious suppression "+2.0 ma" , cpmv 4% "+2.8 ma" , cpmv 4% "+4.0 ma" , cpmv 4% 7.4 "-1.2 ma" , cpmv 6% "-2.0 ma" , cpmv 6% "-2.8 ma" , cpmv 6% "-4.0 ma" 6% 7.8 current mismatch "1.2 ma" , cpmm 0.7 % v pd2 =5v, v cp2 = v pd2 /2 iref=100 a "2.0 ma" , cpmm 1.3 % "2.8 ma" , cpmm 1.8 % "4.0 ma" , cpmm 1.5 %
reference 5 - 6 pmb 2347 preliminary wireless components specification, august 1999 table 5-4 ac/dc characteristics with vcc 1/2 =2.7 .. 5.0 v, ambient temperature t amb = -40c to 85c (continued) sym- bol limit values unit test conditions l item min typ max output rext v rext 9 rext 1.2 v v cc2 = 3.6v, r ext =12k 10.1 i rext , rext 100 a v cc2 = 3.6v, r ext =12k output signal bsw at bsw/ld-pin (n-channel open drain) l-output voltage 9 ol 0.4 v v cc1 = 2.7 - 3.6v, i ol = 0.3 ma fall time w f 310ns v cc1 = 3.6v, c i = 10pf n this value is only guaranteed in lab.
reference 5 - 7 pmb 2347 preliminary wireless components specification, august 1999 5.2 serial control data format timing ? ? ? ? ? ? 9 il 9 ih 9 ih 9 il 9 ih 9 il 9 ih 9 il t whcl w when w ecl w cle w ds w dep clk da en port w f w r t wlcl table 5-5 parameter symbol limit values unit min. max. clock frequency ? cl 15 mhz h-pulsewidth (clk) w whcl 30 ns l-pulsewidth (clk) w wlcl 30 ns data setup w ds 20 ns setup time clock-enable w cle 20 ns setup time enable-clock w ecl 20 ns h-pulsewidth (enable) w when 60 ns rise, fall time t r , t r 10 s propagation delay time en-port w dep 1s
reference 5 - 8 pmb 2347 preliminary wireless components specification, august 1999 5.3 serial control data formats in general each pll can independently be addressed without affecting the other pll (see also test modes). 127( : msb of all serial data is shifted first table 5-6 address of data formats address data format addressed pll a2 a1 a0 0 00 short control data format pll1 (rf) 0 10 long control data format pll1 (rf) 1 00 a-/n-counter pll1 (rf) 1 10 r-counter pll1 (rf) 0 01 short control data format pll2 (if) 0 11 long control data format pll2 (if) 1 01 a-/n-counter pll2 (if) 1 11 r-counter pll2 (if) table 5-7 short control data formats pll 1 pll 2 bit bit function bit bit function lsb 0 0a0 address lsb 01 a0 address 1 0a1 address 10 a1 address 2 0a2 address 20 a2 address 3 c0 ld inactive 3 c0 reserved 4 c1 cp current 2 4 c1 reserved 5 c2 cp current 1 5 c2 cp current 6 msb c3 pllsel 6 msb c3 reserved table 5-8 long control data formats pll 1 pll 2 bit bit function bit bit function lsb 0 0a0 address lsb 01 a0 address 1 1a1 address 11 a1 address 2 0a2 address 20 a2 address 3 c0 ld inactive 3 c0 reserved 4 c1 cp current 2 4 c1 reserved 5 c2 cp current 1 5 c2 cp current 1 6 c3 pllsel 6 c3 data-reg select 7 c4 psc div. ratio 7 c4 psc div. ratio
reference 5 - 9 pmb 2347 preliminary wireless components specification, august 1999 table 5-9 long control data formats (continued) pll 1 pll 2 bit bit function bit bit function 8 c5 reserved 8 c5 reserved 9 c6 cpp width 2 9 c6 cpp width 2 10 c7 cpp width 1 10 c7 cpp width 1 11 c8 standby 2 11 c8 standby 2 12 c9 standby 1 12 c9 standby 1 13 c10 cp polarity 13 c10 cp polarity 14 c11 mode 2 14 c11 reserved 15 c12 mode 1 15 c12 reserved 16 msb c13 sync/async mode 16 msb c13 reserved table 5-10 a/n-counter data formats pll 1 pll 2 bit bit function bit bit function lsb 0 0a0 address lsb 01 a0 address 1 1a1 address 10 a1 address 2 0a2 address 21 a2 address 3 lsb n0 n1-counter 3lsb n0 n2-counter 4 n1 4 n1 5 n2 5 n2 6 n3 6 n3 7 n4 7 n4 8 n5 8 n5 9 n6 9 n6 10 n7 10 n7 11 n8 11 n8 12 n9 12 n9 13 n10 13 n10 14 n11 14 n11 15 n12 15 n12 16 msb n13 16 msb n13 17 lsb ac0 a1-counter 17 lsb ac0 a2-counter 18 ac1 18 ac1 19 ac2 19 ac2 20 ac3 20 msb ac3 21 ac4 22 msb ac5
reference 5 - 10 pmb 2347 preliminary wireless components specification, august 1999 table 5-11 r-counter data formats pll 1 pll 2 bit bit function bit bit function lsb 0 0a0 address lsb 01 a0 address 1 1a1 address 11 a1 address 2 1a2 address 21 a2 address 3 lsb r0 r1-counter 3lsb r0 r2-counter 4 r1 4 r1 5 r2 5 r2 6 r3 6 r3 7 r4 7 r4 8 r5 8 r5 9 r6 9 r6 10 r7 10 r7 11 r8 11 r8 12 r9 12 r9 13 r10 13 r10 14 r11 14 r11 15 r12 15 r12 16 msb msb r13 16 msb msb r13 table 5-12 programming of operation and test modes c12 mode 1 c11 mode 2 c3 pllsel functional mode affected output: pin 11 = bsw/ld 0 00 test 1 fvn1 (pll1) 1 00 test 2 frn1 (pll1) 0 10 reserved frn1 (pll1) 1 10 normal operation, ld of pll1 active lock detect pll1 0 01 test 3 fvn2 (pll2) 1 01 test 4 frn2 (pll2) 0 11 reserved frn2 (pll2) 1 11 normal operation, ld of pll2 active lock detect pll2 table 5-13 programming of cp current of pll1 c2 cp current 1 c1 mode 2 cp current [ma] remark 0 01.2 ma with 100a reference current 1 02.0 ma 0 12.8 ma 1 14.0 ma
reference 5 - 11 pmb 2347 preliminary wireless components specification, august 1999 table 5-14 programming of cp current of pll2 c2 cp current 1 cp current [ma] remark 0 tristate with 100a reference current 1 1.0 ma table 5-15 programming of charge pump pulse width of both plls c7 cpp width 1 c6 cpp width 2 pulse width [ns] typ. remark 0 01.6 ns not recommended for pll2 1 06.0 ns 0 19.0 ns 1 1 13.0 ns table 5-16 standby of power down programming of both plls control bits mode affected output pins z: high impedance (tristate) c9 standby 1 c8 standby 2 pin 11 ld/fo pin 3 cp1 pin 18 cp2 0 0 standby1 off z z 1 0 standby2 off z z 0 1 standby1 off z z 1 1 operation mode active active active table 5-17 programming of synchronous/asynchronous mode of pll1 c13 sync/async synchronous/asynchronous mode 0 asynchronous mode of pll 1 1 synchronous mode of pll 1 table 5-18 programming of pd polarity of both plls control bit pd polarity c10 pd polarity 0 negative polarity 1 positive polarity
reference 5 - 12 pmb 2347 preliminary wireless components specification, august 1999 table 5-19 programming of prescaler divide ratio of both plls control bit prescaler divide ratio c4 psc div. ratio 0 pll1: 32/33 pll2: 8/9 1 pll1: 64/65 pll2: 16/17 table 5-20 programming of pll select control bit pll select c3 of pll1 0 pll1 (rf) 1 pll2 (if) table 5-21 programming of data register select control bits if data register select c3 of pll2 0 data register 1 1 data register 2
reference 5 - 13 pmb 2347 preliminary wireless components specification, august 1999 5.4 input sensitives the following sections show the typical performance at +25c. 1. typical rf sensitivity: the pll setup is: psc:64/65. n:3, a:0, if-pll is in standby mode. 9 && is 2.7 v. the testport open-drain pin is pulled to 2.0 v over 5k1. the cut-off frequency can be increased to typ. >3.45ghz by using a 9 && of 5.0 v 2. typical if sensitivity: the pll setup is: psc:16/17. n:3, a:1,rf-pll is in standby mode. 9 && is 2.7 v. the testport open-drain pin is pulled to 2.0 v over 5k1. . -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 50 300 550 800 1050 1300 1550 1800 2050 2300 2550 2800 3050 3300 ,qsxw)uhtxhqf\>0+]@ , q s x w 3 r z h u > g % p @ baseline topline spec-5.98 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 ,qsxw)uhtxhqf\>0+]@ , q s x w 3 r z h u > g % p @ baseline topline s pec- 5 . 9 8
reference 5 - 14 pmb 2347 preliminary wireless components specification, august 1999 3. typical ri sensitivity: the pll setup is: r:3; rf-pll is in standby mode. 9 && is 3.6v. the testport open-drain pin is pulled to 2.0 v over 5k1. -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 1 6 11 16 21 26 31 36 41 46 ,qsxw)uhtxhqf\>0 +]@ , q s x w 3 r z h u > g % p @ bas +25'c spec-5.98
reference 5 - 15 pmb 2347 preliminary wireless components specification, august 1999 5.5 charge pump currents figure 5-1 definition of charge pump currents terms and abbreviations: v pd supply voltage of charge pump d v src/snk offset voltage from gnd or v pd isnk max maximum sink current @ v pd - d v src isrc max maximum source current @ gnd+ d v snk isnk typ typical sink current @ v pd /2 isrc typ typical source current @ v pd /2 isnk min minimum sink current @ gnd+ d v snk isrc min minimum source current @ v pd - d v src specification of charge pump characteristics: charge pump output magnitude variation cpmv: charge pump current mismatch cpcm: spurious suppression: presuming a standard gsm-application - rf: 900mhz, pd frequency: 200khz, vcc: 2.7v, t a .: -40...+85c - for spurious suppression better than 70db, it is recommendet that d v pd should be within d v snk and v cc - d v snk d v snk v cp v pd /2 isnk max isnk typ isnk min isrc min isrc typ isrc max d v src isnk max isnk min C 2 -------------------------------------------------- - isnk max isnk min + 2 --------------------------------------------------- --------------------------------------------------- - 100% isrc max isrc min C 2 ------------------------------------------------ isrc max isrc min + 2 ------------------------------------------------ - ------------------------------------------------ - 100% isnk typ isrc typ C 2 --------------------------------------------- isnk typ isrc typ + 2 --------------------------------------------- - --------------------------------------------- - 100%
reference 5 - 16 pmb 2347 preliminary wireless components specification, august 1999 5.6 threshold voltages of schmitt-trigger input 7\slfdo9lq7kuhvkrogvri:%xv 0,82 0,92 1,02 1,12 1,22 1,32 2,533,544,55 9&& typ. high min. typ. low max.

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